Peripheral Component Interconnect Express (“PCIe”) is a high-throughput bus standard developed by many technology companies. The specification sets forth a data transmission protocol and system architecture for transferring data. One portion of the PCIe specification sets forth a physical layer (“PHY”) architecture, which isolates the transaction and data link layers from the signaling technology used for link data exchange.
The PHY layer, or physical interface for the PCIE architecture (“PIPE”), is conceptually divided into a physical sub-block and a logical sub-block. The physical sub-block includes a Physical Media Attachment (“PMA”) layer, and the logical sub-block includes a Media Access (“MAC”) layer and a Physical Coding Sublayer (“PCS”). The PCS provides an interface between the MAC and PMA layers. However, the conventional PCS architecture is complex and does not show how to solve the 130 bit block boundary being broken by the variable length skip (“SKP”) ordered set in the PIPE.